In recent years, as one of means for improving the performance of semiconductor devices having a MOS structure, FINFETs, obtained by forming a convex semiconductor layer having a fin shape on a substrate and then forming a gate electrode on a side or upper surface of the semiconductor layer to form a channel region, have been proposed.
For example, a known FINFET is disclosed in J. Kedzierski et al., IEDM Technical Digest pp. 437-440 (2001) (which will be hereinafter referred to as Reference 1).
FIGS. 19(a) and 19(b) are perspective and cross-sectional views illustrating the known FINFET, respectively. As shown in FIGS. 19(a) and 19(b), in the known FINFET, a thin silicon FIN 102 having a thickness of about 20 nm (in the x-axis direction) is formed on a BOX (buried oxide film) 101, i.e., an SOI substrate, so as to be elongate (in the y-axis direction), a gate electrode 103 made of polysilicon is formed so as to lay across the silicon FIN 102 with a gate oxide film 106 interposed between the silicon FIN 102 and the gate electrode 103, and then a source pad 104 and a drain pad 105 are formed.
The FINFET has a double-gate structure in which a gate voltage can be applied from both sides of the silicon FIN shown in FIG. 19(b). Accordingly, in the FINFET, improvement of cutoff properties, suppression of the short channel effect and the like are achieved. Therefore, the FINFET is considered to be effective means for solving problems which arise when the gate length of a MOSFET is reduced.
Moreover, for example, in Reference 1, modified structures of the above-described FINFET are proposed. For example, some structures in which by forming a FIN on a silicon substrate to allow application of a substrate bias, deterioration of the source-drain breakdown voltage due to influence of accumulated holes (in the case of an n-channel FET) which may possibly occur in a fully depleted transistor on an SOI substrate can be suppressed are disclosed in Reference 1.
The structures proposed therein include a structure which is characterized in that an insulating film having an opening portion is formed on a semiconductor substrate and a FIN and a gate electrode are formed in the opening portion and can be fabricated in a simple manner.
FIG. 20(a) is a plan view of an example of the known FINFET disclosed in Reference 1 when the example is viewed from the top. FIG. 20(b) is a cross-sectional view taken along the line XXb-XXb shown in FIG. 20(a). FIG. 20(c) is a cross-sectional view taken along the line XXc-XXc shown in FIG. 20(a).
The known FINFET includes a p-type Si substrate 201 having an active region, source and drain regions 209 and 210 each of which is provided on the active region of the p-type Si substrate 201 and made of a semiconductor containing an n-type impurity, and an LDD regions 208 which are provided so as to be in contact with the source and drain regions 209 and 210, respectively, to face each other and to contain an n-type impurity at a lower concentration than that in the source and drain regions 209 and 210, a convex Si FIN 203 provided on part of the active region of the p-type Si substrate 201 located between the source and drain regions 209 and 210, a gate oxide film 204 provided on side surfaces of the Si FIN 203 as well as the upper surface of the Si FIN 203, a first gate electrode 205 provided on the gate oxide film 204, a second gate electrode 206 provided on the first gate electrode 205, an insulating film 202 which surrounds the active region and is made of SiO2, a gate side wall insulating film 207 provided on a side wall of the first gate electrode 205, an interlevel insulating film 211 provided over the second gate electrode 206, the source region 209 and the drain region 210, and a contact plug 212 which passes through the interlevel insulating film 211 to reach the source region 209 or the drain region 210.
As for methods for forming a FIN, a method in which a FIN is formed by removing the p-type Si substrate 201 by etching, a method in which a FIN is epitaxially grown in a region of the p-type Si substrate 201 corresponding to the opening portion of the insulating film 202, and like method are disclosed.